1. Field of the Invention
The present invention relates to a semiconductor memory device and associated methods. More particularly, the present invention relates to a magnetic memory device having uniform switching characteristics and capable of switching with a low current, a method of operating the same and a method of making the same.
2. Description of the Related Art
A magnetic RAM includes a field effect transistor as a switching device and a magnetic tuneling junction MTJ cell as a data storing unit. The MTJ cell includes a tunneling layer and magnetic layers formed on and under the tuneling layer. The resistance of the MTJ cell varies depending on the magnetization orientations of the magnetic layers formed on and under the tuneling layer. The magnetic RAM utilizes this property of the MTJ cell to store data in the MTJ cell.
FIG. 1 illustrates a sectional view of a conventional magnetic RAM.
Referring to FIG. 1, a conventional magnetic RAM includes a semiconductor substrate 10 and a gate stack structure 12 on the semiconductor substrate 10. The gate stack structure 12 includes a gate electrode. A source region 14 and a drain region 16 are formed on the semiconductor substrate 10 on either side of the gate stack structure 12. The gate stack structure 12, the source region 14 and the drain region 16 form a transistor T. A field oxide layer 11 is on either side of the source and drain regions opposite the gate stack structure 12. An interlayer insulating layer 18 covers the transistor T. A digit line 20 is also formed over the gate stack structure 12. The digit line 20 is covered with the interlayer insulating layer 18 and is formed in parallel with the gate stack structure 12. A contact hole 22 is formed in the interlayer insulating layer 18. The drain region 16 is exposed through the contact hole 22. The contact hole 22 is filled with a conductive plug 24, and the top of the conductive plug 24 is in contact with a pad conductive layer 26 formed on the interlayer insulating layer 18. The pad conductive layer 26 is formed over the digit line 20.
An MTJ structure S is formed on the pad conductive layer 26 and it is aligned with the digit line 20. A second interlayer insulating layer 28 covering the MTJ structure S and the pad conductive layer 26 is formed. A via hole 30 is formed in the second interlayer insulating layer 28 to expose an upper layer of the MTJ structure S. A bit line 32 is formed on the second interlayer insulating layer 28 to fill the via hole 30. The bit line 32 extends across the gate electrode and the digit line 20 in a perpendicular direction.
FIG. 2 illustrates a detailed view of the MTJ structure S.
Referring to FIG. 2, the MTJ structure S includes a seed layer 40 formed on the pad conductive layer 26 and a pinning layer 42, a pinned layer 44, a tunneling oxide layer 48, a free magnetic layer 50, and a capping layer 52 that are sequentially formed on the seed layer 40.
To accurately read data from the magnetic RAM, the magnetic RAM should have a large sensing margin. The sensing margin of the magnetic RAM is determined by a magnetic resistance ratio (MR ratio) of the MTJ structure. In other words, a difference between a minimum resistance and a maximum resistance of the MTJ structure should be large.
To increase the MR ratio of the MTJ structure, it is preferable that the MTJ structure is stable and has a uniform thickness. Particularly, the thickness of the tunneling layer must be uniform. For this, the manufacturing process of the tunneling layer must be stable. Further, good selectivity is required. That is, when a MTJ structure is selected from the magnetic RAM, neighboring MTJ structures should not be affected by the selection.
In the conventional magnetic RAM, however, abnormal phenomena, such as vortex pinning, illustrated in FIG. 3, and domain wall pinning, illustrated in FIG. 4, are present in the free magnetic layer when data is written to the MTJ structure layer or read from the MTJ structure. Vortex pinning and domain wall pinning obstruct a normal switching operation of the free magnetic layer of the MTJ structure. That is, vortex pinning or domain wall pinning significantly increases the magnetic field required for a switching operation of the free magnetic layer, thereby increasing current required for generating the magnetic field.
When vortex pinning or domain wall pinning occurs and a normal amount of current is applied to the MTJ structures, there may be MTJ structures whose free magnetic layers are not switched. These MTJ structures become fail bits.
FIG. 5 illustrates a fail bit ratio resulting from writing data to a conventional magnetic RAM with the MTJ structure depicted in FIG. 2. Referring to FIG. 5, MTJ structures that are not switched under normal switching fields are denoted by C1, C2, C3 and C4. The MTJ structures C1, C2 and C4 are switched by a switching field that is stronger than the normal switch field, and the MTJ structure C3 is switched by a switching field weaker than the normal switch field.
Though vortex pinning can be somewhat decreased by reducing the thickness of the free magnetic layer, such a reduction in thickness significantly lowers the thermal stability of the magnetic moment of the free magnetic layer and thereby increases the MTJ structure's thermal instability.